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Latency Numbers Explorer

MDN Reference

In storage engineering, hardware mechanical sympathy begins with understanding the physical orders of magnitude separating CPU registers from magnetic disks and remote network hops.

⏱️Numbers Every Storage Engineer Should Know

Hardware access times span 8 orders of magnitude. If an L1 cache hit took 1 second, reading from an NVMe SSD is like waiting 5.5 hours, and an HDD seek is like waiting 7.6 months!

L1 Cache Referencecpu
0.5 ns⏳ 1 seconds
Fetching an instruction or scalar from on-die L1 data cache.CPU Core (L1d)
Branch Mispredictcpu
5 ns⏳ 10 seconds
Pipeline flush & speculative execution rewind.Branch Target Buffer
L2 Cache Referencecpu
7 ns⏳ 14 seconds
Fetching from unified L2 core cache (~512KB - 1MB per core).CPU Core (L2)
Mutex Lock / Unlockcpu
25 ns⏳ 50 seconds
Uncontended atomic compare-and-swap (CAS) operation.CPU Cache Coherency (MESI)
Main Memory (DRAM) Accessmemory
100 ns⏳ 3.3 minutes
DDR4/DDR5 memory controller access (CAS latency + transfer).DIMM / Memory Bus
Compress 1KB with Zstandardcpu
2.0 µs⏳ 1.1 hours
Lempel-Ziv + FSE fast compression pass on modern CPU.SIMD / CPU registers
NVMe Gen4 SSD 4KB Random Readstorage
10.0 µs⏳ 5.6 hours
PCIe 4.0 x4 bus traversal + NAND Flash die cell read.NVMe controller + 3D TLC
SATA SSD Random 4KB Readstorage
150.0 µs⏳ 3.5 days
AHCI protocol queue + SATA 6Gbps bus overhead.SATA III Flash SSD
Datacenter Roundtrip (Same DC)network
500.0 µs⏳ 11.6 days
Top-of-rack (ToR) switch hop + NIC interrupt handling.100GbE Optical Fabric
Read 1MB Sequentially (NVMe)storage
250.0 µs⏳ 5.8 days
Continuous DMA streaming at ~4,000 MB/s across multi-channel NAND.PCIe NVMe Gen4
HDD Mechanical Seek + Rotationalstorage
10.0 ms⏳ 7.6 months
Arm actuator movement + platter 7200 RPM rotational delay.Magnetic Platter & Actuator
Transatlantic Network Ping (NYC to London)network
70.0 ms⏳ 4.4 years
Speed of light in fiber optics (~200,000 km/s) across Atlantic seabed.Submarine Optical Cable

The Storage Latency Hierarchy​

In modern computer architecture, memory and storage media form a strict hierarchy governed by the trade-off between access speed, cost per gigabyte, and volatility.

graph TD
    A["CPU Registers (0.5 ns)"] --> B["L1 / L2 / L3 Cache (1 - 20 ns)"]
    B --> C["Main Memory / DRAM (50 - 100 ns)"]
    C --> D["CXL / Persistent Memory (150 - 300 ns)"]
    D --> E["NVMe SSD / PCIe 4.0 / 5.0 (10 - 25 µs)"]
    E --> F["SATA SSD (150 µs)"]
    F --> G["Mechanical HDD (10 ms)"]
    G --> H["Cold Tape Archive (> seconds to minutes)"]

Key Engineering Takeaways​

  1. The DRAM to SSD Chasm: Accessing RAM (~100 ns) is 100x faster than fetching a 4KB block from a cutting-edge NVMe SSD (~10 µs), and 100,000x faster than a rotational HDD seek (~10 ms).
  2. Sequential vs Random I/O: Sequential access allows hardware controllers to trigger hardware prefetching, saturate PCIe lanes, and pipeline requests, outperforming random small I/O by orders of magnitude even on solid-state media.
  3. Network vs Disk Paradox: On modern optical 100 GbE datacenter networks with RDMA (Remote Direct Memory Access), reading memory on a remote server (~5-10 µs) can be faster than issuing a random read to a local SATA SSD (~150 µs).